GPL Classic Amiga system. 16bit data bus. I am interested in porting Minimig to my Spartan3 board, which leads us to the next project, Minimig_wb. There is already an effort to update Minimig to AGA chipset compatibility, current is the older ECS chipset compatibility. I would like to play with this using the Opencores K68 processor core, as that is in Verilog, compared to the VHDL Opencores TG68 processor core used in the DE1/DE2 implementations of Minimig. Going all one language allows to simulate the whole design with free/open-source tools. No free/open-source tools currently do mixed Verilog/VHDL languages, and also I'm interested in Verilator which compiles Verilog into SystemC for much faster simulation. I don't know of equivalent for VHDL that is free/open-source. Versions that include 68k inside the FPGA use TG68, which is VHDL.
would it fit? Perhaps a simple conversion to Wishbone CPU would fit, no additional peripherals added.
I'd like to add the OpenCores.org Wishbone bus to Minimig. While the Altera DE2 version of Minimig uses TG68 a softcore 68K CPU, that part is in VHDL which I'm not very familiar with. I'd want to make things as 32bit data bus as can be. Fully 32bit if possible. There is a Wishbone 68K CPU on opencores (which is 32bit data bus) which might be a suitable replacement for TG68, and also provides ability to hook up numerous peripherals found on Opencores, which could make Minimig_wb an interesting SoC on its own to experiment with. Hmmm, I just learned about aoOCS project on opencores, which claims to be an independent (not Minimig-based) OCS Amiga using Wishbone. Interesting.
My own homebrew project to create a bridge between Opencores' Wishbone bus to Amiga Zorro2/3 bus. Something so I can play with Wishbone peripherals in my Amiga computers, possibly to add a Zorro bus to Minimig or create a replacement for Commodore's SuperBuster chip. Will need adaptor PCBs to connect the FPGA board to the Zorro slot(s).
PLI_VGA
I think it would be interesting to make a Verilog PLI program for simulation, that would open a window on the host computer running simulation that would display the video output of a simulated VGA device. Or perhaps a multi-format (video mode) display that could read contents of video memory inside the simulation, and display contents of overlay buffer, mpeg decoder, etc. that may not be direct RGB framebuffer format dumping out to a VGA D/A converter. Though I do not think that Icarus is fast enough to replace WinUAE, should I or anyone make something like this. Perhaps Verilator would result in something more "usable" using SystemC/C++. Perhaps the Open Virtual Platforms project would be suitable for such a thing. I can't tell for sure, but perhaps something like this already exists?
This project is a PCB and FPGA project to create an FPGA based Classic Amiga accelerator. Acceleration is obtained by either 1: softcore 68K inside FPGA, 2: industry standard PowerPC computer module, or 3: 68K chip on board shaped like the industry standard module to connect to FPGA pins, which will have to understand the difference between 68K board and PowerPC module.
Amiga Zorro3 spec and addendum (board-level point of view), Buster (Zorro bus controller) specs, Amiga CPU slot specs, and other stuff can be found at the Dave Haynie Archives, though I've had to look them up in Wayback Machine before due to site outage.
Zorro2 Developer's Manual, 680x0 datasheets, and other Amiga-ish information can be found at the Amiga Technical Resource.
PowerPC MPC7400 User Manual talks about MPX bus protocol in section 9.6. I guess this continues the MPX bus "spec"
PowerPC™ MPX Bus Implementation Differences doc compares MPC7400, MPC7410, and the MPC7450 implementations. I assume this continues the MPX bus "spec"
OpenCores is a fantastic resource of lots of Open-Source IP blocks and full SoC designs.
GRlib is an Open-Source VHDL library of various IP blocks with a Leon CPU (Sparc compatible), and it has templates and bitfiles for my Spartan3 board! Neat!
OpenSparc is an Open-Source release of Sun's Sparc processor design.
ERC32 is a Sparc7 compatible CPU with Open-Source VHDL.
soc_lm32 is a gpl3 SOC design using wishbone peripherals, interesting to learn from. Done in Verilog.
milkymist SoC is another open-source SOC Design using Wishbone stuff.
Zylin CPU is another open-source CPU for learning.
FPGA64 is a VHDL Commodore64 in an FPGA project. Not libre-open source but sources are available for educational use at no cost. Current version today is closed-source due to inclusion of something called Chameleon.
1541U iuses an FPGA to emulate a Commodore 1541 floppy drive, now microSD or USB flash for storage.
Interesting Specs (to me anyway)
Interesting Projects